HFT CORE SYSTEMS

Curriculum

96 lessons that take you from measurement, probability basics and low-level C++ to Linux, networking, concurrency, market microstructure, market data, order books, execution, risk and a full tick-to-trade capstone.

Preview lesson 01 Course overview

01

HFT ENGINEERING ROADMAP

What you learn, in order.

01Measurement + probability basicsDistributions · percentiles · tail latency · benchmark confidence 02CPU + memory systemsCaches · branch prediction · TLBs · NUMA · memory bandwidth 03Linux for low latencyScheduling · affinity · interrupts · memory · host tuning 04Networking + packet pathsUDP · multicast · sockets · AF_XDP · DPDK · NIC locality 05Low-latency C++Memory layout · allocation · parsing · SIMD · fixed-point types 06Concurrency + lock-free engineeringAtomics · memory ordering · queues · reclamation · contention 07Markets + microstructureOrders · venues · spreads · matching · product vocabulary · order books 08Market data + execution + riskFeeds · sequencing · order entry · executions · limits · reconciliation 09Tick-to-trade + production systemsArchitecture · latency attribution · recovery · observability · operations 10HFT interviews + job preparationC++/DSA coding · systems design · mock interviews · resume + portfolio

ALL 96 LESSONS

Course lessons

SEARCHPHASE

VISIBLE96

PHASE 01

Measurement before optimization

EP 01–08

Define latency like an engineerSeparate service time, queueing time and end-to-end latency

Build a benchmark harness that resists self-deceptionPrevent dead-code elimination and constant folding

Clocks: monotonic time, TSC, RDTSCP, and calibrationChoose between OS clocks, TSC and RDTSCP

Describe the machine before describing the resultCapture CPU, cache, NUMA, kernel and compiler context

Histograms and tails, not averagesRead distributions beyond mean and median

Hardware counters without cargo cultingConnect PMU events to a concrete performance hypothesis

Disassembly as experimental evidenceMap source constructs to generated instructions

Phase gate: the reproducible benchmark laboratoryCombine clocks, manifests, histograms and counters

PHASE 02

CPU and memory systems

EP 09–20

Cache geometry and address decompositionDecompose an address into offset, set and tag

Cache coherence: MESI/MOESI without the bus-lock mythTrace cache-line state transitions between cores

False sharing and constructive sharingDetect independent fields sharing a coherence line

Out-of-order execution and the dependency graphReason about dependencies rather than source order

Branch prediction and data-dependent control flowExplain predictors without treating branches as universally bad

SIMD with feature dispatchRecognize vectorizable data layouts

TLBs and page walksConnect virtual addresses to page-table translation

Huge pages: explicit HugeTLB vs. THPCompare explicit huge pages with transparent huge pages

NUMA placement and ownershipMap CPU and memory locality across NUMA nodes

Prefetching: hardware, software, and pointer chasingKnow where hardware prefetchers succeed

DRAM and memory bandwidth under contentionSeparate memory latency from sustainable bandwidth

Phase gate: data-oriented redesignRedesign a workload around access pattern and ownership

PHASE 03

Linux determinism

EP 21–32

Scheduler classes and real-time hazardsCompare normal and real-time scheduling policies

Affinity, topology, SMT, and migrationPin work to CPUs using topology-aware choices

CPU isolation as a system configurationSeparate application affinity from true CPU isolation

Interrupts, NAPI, softirqs, and NIC queuesTrace receive work from interrupt to softirq

Memory locking and prefaultingExplain page faults on a latency-sensitive path

Power management, turbo, C-states, and thermal behaviorConnect frequency and idle states to latency variance

Finding OS noise with rtla, ftrace, and perfUse tracing to localize latency spikes

System calls and context switches are different thingsSeparate privilege transitions from scheduler switches

Shared memory IPC with explicit ownershipDesign shared-memory layout and initialization

cgroup v2, cpusets, memory nodes, and least privilegeConstrain CPU and memory placement with cgroup v2

Asynchronous logging: page cache, direct I/O, and io_uringKeep formatting and storage off the hot path

Phase gate: reproducible low-jitter host profileCombine placement, memory, IRQ and power controls

PHASE 04

Network datapaths

EP 33–44

Ethernet frames and the real wire budgetAccount for preamble, headers, FCS and inter-packet gap

IPv4/IPv6, UDP, checksums, and fragmentationParse IP and UDP headers safely

Multicast joins, IGMP, and feed topologyUnderstand group membership and IGMP behavior

The Linux receive path: DMA to userspaceTrace buffer ownership from NIC DMA to recvmsg

Socket tuning and busy pollingSize socket buffers from traffic and burst assumptions

RSS, flow steering, RPS/RFS, and XPSMap flows to NIC queues and CPUs

AF_PACKET, PACKET_MMAP, and AF_XDPCompare socket, mmap ring and XDP data paths

DPDK architecture and memory ownershipUnderstand EAL, huge pages, mbufs and poll-mode drivers

AMD Solarflare ef_vi and raw layer-2 accessUnderstand virtual interfaces and event queues

PCIe, DMA, IOMMU, DDIO, and NIC localityTrace NIC DMA across PCIe and the IOMMU

Hardware and software packet timestampsDistinguish application, kernel and NIC timestamp points

Phase gate: receiver bake-offCompare receive paths under identical traffic

PHASE 05

Low-latency C++

EP 45–56

Object lifetime, storage, alignment, and aliasingSeparate storage duration from object lifetime

Value categories, moves, forwarding, and copy elisionReason about lvalues, xvalues and prvalues

Layout by access pattern, not packingChoose AoS, SoA and hybrid layouts by access pattern

Allocation strategy: arenas, PMR, pools, and failure policyChoose an allocator by lifetime and capacity

Fixed-capacity text and identifiersRepresent bounded strings without hidden allocation

Static polymorphism, concepts, and devirtualizationReplace runtime dispatch only where variants are known

Inlining, branch hints, LTO, PGO, and code layoutTreat inlining as a cost model, not a keyword

Exceptions, RTTI, noexcept, and error channelsChoose error channels by failure domain

Containers under latency constraintsEvaluate containers by allocation, locality and iterator stability

Fixed-point money and quantity typesAvoid floating-point ambiguity in price and quantity

Safe, allocation-free binary parsingValidate bounds before reading untrusted bytes

Phase gate: allocation-free protocol coreCombine bounded types, storage and parsing

PHASE 06

Concurrency and lock-free engineering

EP 57–68

The C++ memory model and data-race freedomDefine happens-before and conflicting actions

Sequential consistency and total orderExplain the single order promised by seq_cst

Acquire/release publicationPublish initialized state with release

Relaxed atomics, counters, and misconceptionsUse relaxed operations when only atomicity is required

SPSC ring buffer from invariants firstDefine ownership of slots and indices

Bounded MPMC queues and sequence numbersCoordinate multiple producers and consumers per slot

Michael–Scott queue and linked-node trade-offsLocate enqueue and dequeue linearization points

Spinlocks, atomic_wait, futexes, and backoffChoose spinning, parking or hybrid waiting by hold time

ABA: mechanism, not sloganConstruct an execution where A changes and returns

Hazard pointers and safe reclamationPublish protected pointers before dereference

Epoch reclamation and user-space RCUUnderstand grace periods and reader quiescence

Phase gate: queue library and concurrency defensePackage bounded queues behind explicit contracts

PHASE 07

Electronic trading systems

EP 69–80

Market microstructure for systems engineersUnderstand venues, participants, matching and price-time priority

Feed transport, packet headers, and sequencingParse feed packet and message framing

Nasdaq ITCH decoding with schema disciplineTranslate a wire specification into typed messages

Feed arbitration, gap detection, and recoveryArbitrate redundant A/B feeds deterministically

L1, L2, and L3 limit-order-book designDistinguish top-of-book, aggregated depth and order-level state

Book data structures by instrument domainChoose dense, sparse or hybrid price-level storage

FIX tag-value, FAST, and SBE are different toolsCompare human-readable, compressed and fixed-schema protocols

Order entry: OUCH lifecycle and session stateModel login, sequence and session transitions

Pre-trade risk as a controlled systemEnforce quantity, notional, position and rate limits

Order management, drop copy, and reconciliationMaintain authoritative order and execution state

Deterministic replay and exchange simulationCapture inputs needed to reproduce a run

Phase gate: market-data plant and order gatewayConnect sequencing, decoding, book and order state

PHASE 08

Production safety and operations

EP 81–88

PTP, PHC, clock domains, and timestamp provenanceUnderstand PTP roles and NIC hardware clocks

End-to-end latency attributionDefine timestamps at each processing boundary

Capacity, backpressure, and overload policyModel arrival rate, service rate, burst and queue capacity

Journaling, durability, and crash recoveryDefine what must survive which failure

Failure injection and chaos for a single hostTurn assumptions into explicit fault experiments

Observability that stays off the critical pathSeparate hot-path event capture from cold-path aggregation

Deployment, warm-up, rollout, and rollbackMake artifacts, configuration and host state reproducible

Incident response and postmortemsStabilize before diagnosing deeply

PHASE 09

Capstone and hiring conversion

EP 89–96

Architecture of the integrated tick-to-trade platformPartition feed, book, strategy, risk and gateway responsibilities

Integrate the hot path without hiding copiesTrace every buffer and representation transition

End-to-end correctness campaignTest invariants across component boundaries

End-to-end performance campaignBenchmark the complete path under realistic traffic

Design review: defend the trade-offsExplain why each major design fits the workload

Incident game day and recovery demonstrationOperate the system while faults compound

HFT interview loop simulationAnswer C++, systems and market-structure questions from first principles

Portfolio launch and engineering retrospectivePackage the repositories for a five-minute reviewer journey