Learning objectives
What you should understand
- Trace NIC DMA across PCIe and the IOMMU
- Relate DDIO and cache pressure to receive behavior
- Place NIC, memory and polling CPU by topology
Lab
Hands-on exercise
Map a host's NIC PCIe path and NUMA locality.
Deliverable
Evidence of completion
A hardware-topology diagram with an evidence-based placement recommendation.
- Prerequisite
- EP 41