HFT CORE SYSTEMS

TLBs and page walks

Lesson 15 of 96Phase 02: CPU and memory systems
Video lesson coming soon

The written objectives and hands-on lab are available now.

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Learning objectives

What you should understand

  1. Connect virtual addresses to page-table translation
  2. Distinguish cache misses from TLB misses
  3. Predict when working-set size pressures the TLB

Lab

Hands-on exercise

Sweep page count and access order to expose translation cost.

Deliverable

Evidence of completion

A page-walk experiment with TLB counter evidence.

Prerequisite
EP 14

Phase 02

CPU and memory systems

Full curriculum