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HFT Core Systems

HFT CORE SYSTEMS

Cache geometry and address decomposition

Lesson 09 of 96Phase 02: CPU and memory systems
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The written objectives and hands-on lab are available now.

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Learning objectives

What you should understand

  1. Decompose an address into offset, set and tag
  2. Predict conflicts from cache geometry
  3. Relate associativity and working-set shape to misses

Lab

Hands-on exercise

Construct a stride experiment that reveals cache-set conflicts.

Deliverable

Evidence of completion

A cache-geometry diagram plus measured conflict-miss curve.

Prerequisite
EP 08

Phase 02

CPU and memory systems

Full curriculum
09Cache geometry and address decomposition10Cache coherence: MESI/MOESI without the bus-lock myth11False sharing and constructive sharing12Out-of-order execution and the dependency graph13Branch prediction and data-dependent control flow14SIMD with feature dispatch15TLBs and page walks16Huge pages: explicit HugeTLB vs. THP17NUMA placement and ownership18Prefetching: hardware, software, and pointer chasing19DRAM and memory bandwidth under contention20Phase gate: data-oriented redesign