cppvalleyC++ · Systems · Low Latency · HFT
HFT Core Systems

HFT CORE SYSTEMS

SIMD with feature dispatch

Lesson 14 of 96Phase 02: CPU and memory systems
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The written objectives and hands-on lab are available now.

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Learning objectives

What you should understand

  1. Recognize vectorizable data layouts
  2. Write portable scalar fallbacks and ISA-specific paths
  3. Dispatch safely by runtime CPU capability

Lab

Hands-on exercise

Implement scalar and SIMD decoders with identical correctness tests.

Deliverable

Evidence of completion

A feature-dispatched benchmark with assembly and speedup limits.

Prerequisite
EP 13

Phase 02

CPU and memory systems

Full curriculum
09Cache geometry and address decomposition10Cache coherence: MESI/MOESI without the bus-lock myth11False sharing and constructive sharing12Out-of-order execution and the dependency graph13Branch prediction and data-dependent control flow14SIMD with feature dispatch15TLBs and page walks16Huge pages: explicit HugeTLB vs. THP17NUMA placement and ownership18Prefetching: hardware, software, and pointer chasing19DRAM and memory bandwidth under contention20Phase gate: data-oriented redesign